Communication developments in the last decade have demonstrated what seems to be a migration from parallel data input/output (I/O) interface implementations to a preference for serial data I/O interfaces. Some of the motivations for preferring serial I/O over parallel I/O include reduced system costs through reduction in pin count, simplified system designs, and scalability to meet the ever increasing bandwidth requirements of today's communication needs. Serial I/O solutions will most probably be deployed in nearly every electronic product imaginable, including IC-to-IC interfacing, backplane connectivity, and box-to-box communications.
As the migration to serial communication devices proliferates, so does the demand for higher bandwidth. As the data bandwidth increases, however, data propagation losses through integrated circuit (IC) packaging becomes increasingly predominant. Thus, scattering parameter (S-parameter) techniques are generally required to accurately simulate high-data rate, e.g., 10 Gbps, serial data paths through today's high performance IC packaging, such as for example, ball grid array (BGA) packaging. S-Parameter techniques may also be used to characterize the effects of components within these high performance packages, such as connectors, blocking capacitors, etc.
Integrating high-data rate serial data paths with internal IC logic, however, typically requires the use of a serializer/deserializer (SERDES) device to convert the incoming serial data into a parallel data path and to convert the outgoing parallel data into a serial data path. Thus, in order to properly simulate SERDES operations, S-parameter simulation models are typically combined with complex SERDES simulation models.
The combination of SERDES and S-parameter simulation models typically results in a simulation model that is burdened with a large number of input/output (I/O) ports. Increasing the number of I/O ports of a particular simulation file, however, increases the amount of time required to properly simulate the device. Thus, simulation operations requiring a large number of computations, such as the generation of an eye diagram, may require an excessive amount of time to complete.
One method to decrease the amount of simulation time required, is to increase the amount of computational power that is available within the simulation platform being utilized. Such a method, however, may be cost prohibitive or simply unavailable. Efforts continue, therefore, to reduce the complexity of the simulation files, while maintaining an accurate representation of the device model so as to create accurate simulation results in less time.